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TC58BVG0S3HTAI0 2012-08-31c 1 toshiba mos digital integrated circuit silicon gate cmos 1 gbit (128m 8 bit) cmos nand e 2 prom description the TC58BVG0S3HTAI0 is a single 3.3v 1 gbit (1 ,107,296,256 bits) nand electrically erasable and programmable read-only memory (nand e 2 prom) organized as (2048 + 64) bytes 64 pages 1024blocks. the device has a 2112-byte static register which allows program and read data to be transferred between the register and the memory cell array in 2112-bytes increments. the erase operation is implemented in a single block unit (128 kbytes + 4 kbytes: 2112 bytes 64 pages). the TC58BVG0S3HTAI0 is a serial-type memory device wh ich utilizes the i/o pins for both address and data input/output as well as for command in puts. the erase and program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recordin g, image file memory for still cameras and other systems which require high-d ensity non-volatile memory data storage. the TC58BVG0S3HTAI0 has ecc logic on the chip and 8bit read errors for each 528bytes can be corrected internally. features ? organization x8 memory cell array 2112 64k 8 register 2112 8 page size 2112 bytes block size (128k + 4k) bytes ? modes read, reset, auto page program, auto block erase, status read, page copy, ecc status read ? mode control serial input/output command control ? number of valid blocks min 1004 blocks max 1024 blocks ? power supply v cc = 2.7v to 3.6v ? access time cell array to register 40 s typ. serial read cycle 25 ns min (cl=50pf) ? program/erase time auto page program 330 s/page typ. auto block erase 2.5 ms/block typ. ? operating current read (25 ns cycle) 30 ma max. program (avg.) 30 ma max erase (avg.) 30 ma max standby 50 a max ? package tsop i 48-p-1220-0.50 (weight: 0.53 g typ.) ? 8bit ecc for each 528bytes is implemented on a chip.
TC58BVG0S3HTAI0 2012-08-31c 2 pin assignment (top view) pin names i/o1 to i/o8 i/o port ce chip enable we write enable re read enable cle command latch enable ale address latch enable wp write protect by/ ry ready/busy v cc power supply v ss ground nc no connection nc nc nc nc i/o8 i/o7 i/o6 i/o5 nc nc nc v cc v ss nc nc nc i/o4 i/o3 i/o2 i/o1 nc nc nc nc 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 nc nc nc nc nc nc by/ry re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc nc nc 8 8 TC58BVG0S3HTAI0
TC58BVG0S3HTAI0 2012-08-31c 3 block diagram absolute maximum ratings symbol rating value unit v cc power supply voltage ? 0.6 to 4.6 v v in input voltage ? 0.6 to 4.6 v v i/o input /output voltage ? 0.6 to v cc + 0.3 ( 4.6 v) v p d power dissipation 0.3 w t solder soldering temperature (10 s) 260 c t stg storage temperature ? 55 to 150 c t opr operating temperature -40 to 85 c capacitance * (ta = 25c, f = 1 mhz) symb0l parameter condition min max unit c in input v in = 0 v ? 10 pf c out output v out = 0 v ? 10 pf * this parameter is periodically samp led and is not tested for every device. i/o control circuit status register command register column buffer column decoder data register 0 sense amp memory cell array control circuit hv generator row address decoder logic control by/ry v cc i/o1 v ss ce cle ale we re by/ry row address buffer decoder to wp ecc logic address register data register 1 i/o8
TC58BVG0S3HTAI0 2012-08-31c 4 valid blocks symbol parameter min typ. max unit n vb number of valid blocks 1004 ? 1024 blocks note: the device occasionally contains unus able blocks. refer to application note (13) toward the end of this document. the first block (block 0) is guaranteed to be a valid block at the time of shipment. the specification for the minimum number of valid blocks is applicable over lifetime recommended dc operating conditions symbol parameter min typ. max unit v cc power supply voltage 2.7 ? 3.6 v v ih high level input voltage vcc x 0.8 ? v cc + 0.3 v v il low level input voltage ? 0.3 * ? vcc x 0.2 v * ? 2 v (pulse width lower than 20 ns) dc characteristics (ta = -40 to 85 ? , v cc = 2.7 to 3.6v) symbol parameter condition min typ. max unit i il input leakage current v in = 0 v to v cc ? ? 10 a i lo output leakage current v out = 0 v to v cc ? ? 10 a i cco1 serial read current ce = v il , i out = 0 ma, tcycle = 25 ns ? ? 30 ma i cco2 programming current ? ? ? 30 ma i cco3 erasing current ? ? ? 30 ma i ccs standby current ce = v cc ? 0.2 v, wp = 0 v/v cc , ? ? 50 a v oh high level output voltage i oh = ? 0.1 ma vcc ? 0.2 ? ? v v ol low level output voltage i ol = 0.1 ma ? ? 0.2 v i ol ( by/ ry ) output current of by/ry pin v ol = 0.2 v ? 4 ? ma
TC58BVG0S3HTAI0 2012-08-31c 5 ac characteristics and recommended operating conditions (ta = -40 to 85 ? , v cc = 2.7 to 3.6v) symbol parameter min max unit t cls cle setup time 12 ? ns t clh cle hold time 5 ? ns t cs ce setup time 20 ? ns t ch ce hold time 5 ? ns t wp write pulse width 12 ? ns t als ale setup time 12 ? ns t alh ale hold time 5 ? ns t ds data setup time 12 ? ns t dh data hold time 5 ? ns t wc write cycle time 25 ? ns t wh we high hold time 10 ? ns t ww wp high to we low 100 ? ns t rr ready to re falling edge 20 ? ns t rw ready to we falling edge 20 ? ns t rp read pulse width 12 ? ns t rc read cycle time 25 ? ns t rea re access time ? 20 ns tcea ce access time ? 25 ns t clr cle low to re low 10 ? ns t ar ale low to re low 10 ? ns t rhoh re high to output hold time 25 ? ns t rloh re low to output hold time 5 ? ns t rhz re high to output high impedance ? 60 ns t chz ce high to output high impedance ? 20 ns t csd ce high to ale or cle don?t care 0 ? ns t reh re high hold time 10 ? ns t ir output-high-impedance-to- re falling edge 0 ? ns t rhw re high to we low 30 ? ns t whc we high to ce low 30 ? ns t whr we high to re low 60 ? ns t wb we high to busy ? 100 ns t rst device reset time (ready/read/program/erase) ? 5/5/10/500 s *1: tcls and tals can not be shorter than twp *2: tcs should be longer than twp + 8ns.
TC58BVG0S3HTAI0 2012-08-31c 6 ac test conditions condition parameter v cc : 2.7 to 3.6v input level vcc-0.2v, 0.2v input pulse rise and fall time 3 ns input comparison level vcc / 2 output data comparison level vcc / 2 output load c l (50 pf) + 1 ttl note: busy to ready time depends on the pull-up resistor tied to the by/ ry pin. (refer to application note (9) toward the end of this document.) programming / erasing / reading characteristics (ta = -40 to 85 ? , v cc = 2.7 to 3.6v) symbol parameter min typ. max unit notes t prog average programming time ? 330 700 s n number of partial program cycles in the same page ? ? 4 (1) t berase block erasing time ? 2.5 5 ms tr memory cell array to starting address ? 40 120 s (1) refer to application note (12) toward the end of this document. data output when treh is long, output buffers are disabled by /re=high, and the hold time of da ta output depend on trhoh (25ns min). on this condition, wavefo rms look like normal serial read mode. when treh is short, output buffers are not disabled by /re=high, and the hold time of data output depend on trloh (5ns min). on this condition, output buffers are disabled by the rising edge of cle,ale,/ce or falling edge of /we, and waveforms look like extended data output mode.
TC58BVG0S3HTAI0 2012-08-31c 7 timing diagrams latch timing diagram for command/address/data command input cycle timing diagram cle ale ce re we hold time t dh setup time t ds i/o : v ih or v il t cs t dh t ds t als t alh t wp t cls t ch t clh : v ih or v il ce cle we ale i/o
TC58BVG0S3HTAI0 2012-08-31c 8 address input cycle timing diagram data input cycle timing diagram we t wp t wp t wh t wp t als t wc t dh t ds d in 0 d in 1 t clh t ch ale cle ce i/o d in 2111 t dh t ds t dh t ds t cs t cls t ch t cs t alh pa8 to 15 ca8 to 11 : v ih or v il t dh t ds t cls cle t als t alh t wp t wh t wp ca0 to 7 t dh t ds t cs t cs we ale i/o t dh t ds t wp t wh t dh t ds t wp t wh t wc pa0 to 7 t clh t ch t ch ce
TC58BVG0S3HTAI0 2012-08-31c 9 serial read cycle timing diagram status read cycle timing diagram t reh t chz ce t rhz t rea t rc t rr t rhz t rea t rhz t rea re by/ry i/o t rhoh t rhoh t rhoh t rp t rp t rp : v ih or v il t cea t cea : v ih or v il * : 70h represents the hexadecimal number t rhoh t whr we t dh t ds t cls t clr t cs t clh t ch t wp status output 70h* t whc t ir t rea t rhz t chz ce cle re by/ry i/o t cea
TC58BVG0S3HTAI0 2012-08-31c 10 ecc status read cycle timing diagram : v ih or v il * : 7ah represents the hexadecimal number t whr we t dh t ds t cls t clr t cs t clh t ch t wp status output 7ah* t whc t ir t re a ce cle re by/ry i/o t cea status output t re a status output t re a status output t re a sector1 sector2 sector3 sector4
TC58BVG0S3HTAI0 2012-08-31c 11 read cycle timing diagram read cycle timing diagram: when interrupted by ce t clr pa8 to 15 pa0 to 7 ca8 to 11 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea col. add. n data out from col. add. n 00h d out n d out n + 1 by/ry t clr 30h 70h 00h status output t clr t clr 30h pa8 to 15 pa0 to 7 ca8 to 11 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea col. add. n 00h d out n d out n + 1 by/ry t chz t rhz t rhoh col. add. n t csd 70h 00h status output
TC58BVG0S3HTAI0 2012-08-31c 12 column address change in read cycle timing diagram (1/2) continues from of next page 1 i/o t cs t cls t clh t ch t wc t als t alh t r cle ce ale re t dh t ds t dh t ds t alh t wb t cs t cls t clh t ch t als page address p 00h ca0 to 7 t dh t ds ca8 to 11 t dh t ds pa0 to 7 t dh t ds pa8 to 15 t dh t ds 30h we by/ry page address p column address a d out a d out a + 1 70h status output 00h t rc 1 d out a +n t rea t clr t clr
TC58BVG0S3HTAI0 2012-08-31c 13 column address change in read cycle timing diagram (2/2) i/o t cs t cls t clh t ch 05h ca0 to 7 ca8 to 11 t wc t als t alh cle ce ale re t dh t ds t dh t ds t dh t ds column address b e0h t dh t ds t alh t cs t cls t clh t ch t als t rea d out a + n t rhw page address p column address b t rc t clr tcea t ir d out b + n? d out b + 1 d out b 1 continues from of last page 1 we by/ry t whr
TC58BVG0S3HTAI0 2012-08-31c 14 data output timing diagram command i/o t dh t rp t rp we cle ce ale re t rloh t reh t rea t rhz t rea t cs t cls t clh t ch t rp t rr t rloh t ds by/ry t chz t rhoh t rhoh t cea dout dout t alh t rea t rc dout
TC58BVG0S3HTAI0 2012-08-31c 15 auto-program operation timing diagram : v ih or v il : do not input data while data is being output. * ) m: up to 2111 ca0 to 7 t cls t cls t als t ds t dh we cle ce ale re by/ry t clh t ch t cs t ds t dh t alh i/o t cs t dh t ds t dh t prog t wb t ds t alh t als column address n ca8 to 11 d in n d in m* 10h 70h status output pa0 to 7 pa8 to 15 80h d in n+1 t rw
TC58BVG0S3HTAI0 2012-08-31c 16 auto block erase timing diagram t cs 60h pa8 to 15 we cle ce ale re by/ry : v ih or v il t cls t clh t cls pa0 to 7 t ds t dh t als : do not input data while data is being output. auto block erase setup command i/o d0h 70h t wb t berase busy status read command erase start command status output t alh
TC58BVG0S3HTAI0 2012-08-31c 17 copy back program with random data input we cle re i/ox ale ce t wc t wb ry/by col add1 00h 35h col add2 row add1 row add2 col add1 col add2 row add1 data1 datan 10h 70h i/o row add2 t r busy busy t wb t whr copy back program data input command i/o1=0 successful program i/o1=1 error in program read status command column address row address column address row address 70h 00h i/o data1 datan 85h i/o1=0 successful read i/o1=1 error in read
TC58BVG0S3HTAI0 2012-08-31c 18 id read operation timing diagram : v ih or v il we cle re t cea ce ale i/o t ar id read command address 00 maker code device code t rea t cls t cs t ds t ch t alh t als t cls t cs t ch t alh t dh 90h 00h 98h t rea f1h t rea t rea see table 5 see table 5 t rea see table 5 3rd data 4th data 5th data
TC58BVG0S3HTAI0 2012-08-31c 19 pin functions the device is a serial access memory which utiliz es time-sharing input of address information. command latch enable: cle the cle input signal is used to control loading of the operation mode command into the internal command register. the command is latched into the command regi ster from the i/o port on the rising edge of the we signal while cle is high. address latch enable: ale the ale signal is used to control loading address in formation into the internal address register. address information is latched into the address register from the i/o port on the rising edge of we while ale is high. chip enable: the device goes into a low-power standby mode when ce goes high during the device is in ready state. the ce signal is ignored when device is in busy state ( by/ry = l), such as during a program or erase or read operation, and will not enter standby mode even if the ce input goes high. write enable: the we signal is used to control the acqu isition of data from the i/o port. read enable: the re signal controls serial data output. data is available t rea after the falling edge of re . the internal column address counter is also increme nted (address = address + l) on this falling edge. i/o port: i/o1 to 8 the i/o1 to 8 pins are used as a port for transferring address, command and input/ output data to and from the device. write protect: the wp signal is used to protect the de vice from accidental programming or erasing. the internal voltage regulator is reset when wp is low. this signal is usua lly used for protecting the data during the power-on/off sequence when input signals are invalid. ready/busy: the by/ry output signal is used to indicate th e operating condition of the device. the by/ry signal is in busy state ( by/ry = l) during the program, erase and read operations and will return to ready state ( by/ry = h) after completion of the operation. the output buff er for this signal is an open drain and has to be pulled-up to vccq with an appropriate resister. ce we re wp by/ry
TC58BVG0S3HTAI0 2012-08-31c 20 schematic cell layout and address assignment the program operation works on page units wh ile the erase operation works on block units. a page consists of 2112 bytes in which 2048 bytes are used for main memory storage and 64 bytes are for redundancy or for other uses. 1 page = 2112bytes 1 block = 2112 bytes 64 pages = (128k + 4k) bytes capacity = 2112 bytes 64pages 1024 blocks an address is read in via the i/o port over four consecutive clock cycles, as shown in table 1. table 1. addressing i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 first cycle ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second cycle l l l l ca11 ca10 ca9 ca8 third cycle pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ca0 to ca11: column address pa0 to pa15: page address pa6 to pa15: block address pa0 to pa5: nand address in block fourth cycle pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 2112 65536 pages 1024 blocks 2048 2048 64 64 page buffe r data cache i/o8 i/o1 64 pages = 1 block 8i/o
TC58BVG0S3HTAI0 2012-08-31c 21 operation mode: logic and command tables the operation modes such as program, erase, read and reset are controlled by command operations shown in table 3. address input, comma nd input and data input/output are controlled by the cle, ale, ce , we , re and wp signals, as shown in table 2. table 2. logic table cle ale ce we re wp * 1 command input h l l h * data input l l l h h address input l h l h * serial data output l l l h * during program (busy) * * * * * h during erase (busy) * * * * * h * * h * * * during read (busy) * * l h ( * 2) h ( * 2) * program, erase inhibit * * * * * l standby * * h * * 0 v/v cc h: v ih , l: v il , * : v ih or v il * 1: refer to application note (10) toward the end of this document regarding the wp signal when program or erase inhibit * 2: if ce is low during read busy, we and re must be held high to avoid unintended co mmand/address input to the device or read to device. reset or status read command can be input during read busy.
TC58BVG0S3HTAI0 2012-08-31c 22 table 3. command table (hex) first set second set acceptable while busy serial data input 80 ? read 00 30 column address change in serial data output 05 e0 auto page program 80 10 column address change in serial data input 85 ? read for copy-back without data out 00 35 copy-back program without data out 85 10 auto block erase 60 d0 id read 90 ? status read 70 ? { ecc status read 7a ? reset ff ? { table 4. read mode operation states cle ale ce we re i/o1 to i/o8 power output select l l l h l data output active output deselect l l l h h high impedance active h: v ih , l: v il hex data bit assignment (example) 1 0 0 0 0 0 0 0 8765432i/o1 serial data input: 80h
TC58BVG0S3HTAI0 2012-08-31c 23 device operation read mode read mode is set when the "00h" and ?30h? commands are issued to th e command register. between the two commands, a start address for the read mode needs to be issued. after initial power on sequence, ?00h? command is latched into the internal command register. therefore read operation after power on sequence is executed by the setting of only fo ur address cycles and ?30h? command. refer to the figures below for the sequence and the block diagram (refer to the detailed timing chart.). random column address change in read cycle a data transfer operation from the cell array to the data cache via page buffer starts on the rising edge of we in the 30h command input cycle (after the address information has been latched). the device will be in the busy state during this transfer period. after the transfer period, the device returns to ready state. serial data can be output synchronously with the re clock from the start address designated in the address input cycle. cell array select page n m m data cache page buffer i/o1 to 8: m = 2111 select page n m m? during the serial data output from the register, the column address can be changed by inputting a new column address using the 05h and e0h commands. the data is read out in serial starting at the new column address. random column address change operation can be done multiple times within the same page. by/ry we cle re 00h ce ale i/o busy 30h page address n column address m m m+1 m+2 page address n t r start-address input 70h 00h status start-address input by/ry we cle 00h ce ale i/o col. m page n busy page n 30h 05h e0h col. m? m m + 1 m? m? + 1 m? + 2m? + 3m? + 4 page n col. m start from col. m start from col. m? t r m + 2m + 3 re 70h status 00h
TC58BVG0S3HTAI0 2012-08-31c 24 ecc & sector definition for ecc internal ecc logic generates error co rrection code during busy time in program operation. the ecc logic manages 9bit error detection and 8bit error correction in each 528bytes of main data and spare data. a section of main field (512bytes) and spare field (16bytes) are pa ired for ecc. during read, the device executes ecc of itself. once read operation is executed, read status co mmand (70h) can be issued to check the read status. the read status remains until other valid commands are executed. to use ecc function, below limitation must be considered. - a sector is the minimum unit for program operation an d the number of program per page must not exceed 4. 1st main 2nd main 3rd main 4th main 1st spare 2nd spare 3rd spare 4th spare 512b 512b 512b 512b 16b 16b 16b 16b note) internal ecc manages all data of main area and spare area column address (byte) sector main field spare field 1st sector 0 ~ 511 2,048 ~ 2,063 2nd sector 512 ~ 1,023 2,064 ~ 2,079 3rd sector 1,024 ~ 1,535 2,080 ~ 2,095 4th sector 1,536 ~ 2,047 2,096 ~ 2,111 2kbyte page assignment definition of 528byte sector
TC58BVG0S3HTAI0 2012-08-31c 25 auto page program operation the device carries out an automatic page program operation when it receives a "10h" program command after the address and data have been input. the sequence of command, address and data input is shown below. (refer to the detailed timing chart.) random column address change in auto page program operation the column address can be changed by the 85h command duri ng the data input sequence of the auto page program operation. two address input cycles after the 85h command are recognized as a new column address for the data input. after the new data is input to the new column address, the 10h command initiates the actual data program into the selected page automatically. the random column address ch ange operation can be repeated multiple times within the same page. the data is transferred (programmed) from the data cache via the page buffer to the selected page on the rising edge of we following input of the ?10h? command. after programming, the programmed data is transferred back to the page buffer to be automatically verified by the device. if the programming does not succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. selected page program data input read& verification data input selected page readin g & verification program col. m col. m? 80h page n col. m 85h din din 10h status din din din din col. m? din din 70h bus y cle 80h ale i/o page p ce we col. m din 10h 70h din din din data status out re busy by/ry
TC58BVG0S3HTAI0 2012-08-31c 26 auto block erase the auto block erase operation st arts on the rising edge of we after the erase start command ?d0h? which follows the erase setup command ?60h?. this two-cycle process for erase oper ations acts as an extra layer of protection from accidental erasure of data due to external noise. the de vice automatically executes the erase and verify operations. pass i/o fail by/ry 60 d0 70 block address input: 2 cycles status read command busy erase start command
TC58BVG0S3HTAI0 2012-08-31c 27 read for copy-back with da ta output timing guide copy-back operation is a sequence execution of read for copy-back and of copy-back program with the destination page address. a read operation with ?35h ? command and the address of source page moves the whole 2112 bytes data into the internal data buffer. bit errors are checked by sequential reading the data or by reading the status in read after read busy time(tr) to check if uncorrectable error occurs. in the case where there is no bit error or no uncorrectable error, the data don?t need to be reloaded. therefore copy-back program operation is initiated by issuing page-copy data-input command (85h) with destination page address. acutual programming operation begins after program confirm command (10h) is issued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system contoller can detect the completion of a program cycle by monitoring the by/ry output, or the status bit (i/o7) of the status register. when the co py-back program is complete, the write status bit (i/o1) may be checked. the command register remains in read status command mode until another valid command is written to the command register. during copy-back program, data modifi cation is possible using random data input command (85h) as shown below. page copy-back program operation page copy-back program operation with random data input col. add.1,2 & page add.1,2 source address i/ox 00h add.(4cycles) tr 35h i/ox col. add.1,2 & page add.1,2 destination address tprog data output 85h add.(4cycles) data 85h add.(2cycles) data 10h 70h there is no limitation for the number of repetition. i/o1 pass fail ?1? ?0? 70h a a a a 00h col. add.1,2 & page add.1,2 source address i/ox 00h add.(4cycle ) i/o1 pass fail ?1? ?0? col. add.1,2 & page add.1,2 destination address tr tprog 35h data output 85h add.(4cycle ) 10h 70h i/o1 pass fail ?1? ?0? 00h 70h col. add.1,2 by/ry by/ry by/ry
TC58BVG0S3HTAI0 2012-08-31c 28 id read the device contains id codes which can be used to iden tify the device type, the ma nufacturer, and features of the device. the id codes can be read out under the following timing conditions: table 5. code table description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 1st data maker code 1 0 0 1 1 0 0 0 98h 2nd data device code 1 1 1 1 0 0 0 1 f1h 3rd data chip number, cell type 1 0 0 0 0 0 0 0 80h 4th data page size, block size 0 0 0 1 0 1 0 1 15h 5th data plane number 1 1 1 1 0 0 1 0 f2h 3rd data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 internal chip number 1 2 4 8 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 reserved 1 0 0 0 3rd data 90h 00h 98h f1h see table 5 see table 5 we cle re t cea ce ale i/o t ar t re a id read command address 00 maker code device code 4th data 5th data see table 5
TC58BVG0S3HTAI0 2012-08-31c 29 4th data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 page size (without redundant area) 1 kb 2 kb 4 kb 8 kb 0 0 1 1 0 1 0 1 block size (without redundant area) 64 kb 128 kb 256 kb 512 kb 0 0 1 1 0 1 0 1 i/o width x8 x16 0 1 reserved 0 0 1 5th data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 plane number 1 plane 2 plane 4 plane 8 plane 0 0 1 1 0 1 0 1 ecc engine on chip with ecc engine 1 reserved 1 1 1 1 0
TC58BVG0S3HTAI0 2012-08-31c 30 status read the device automatically implements the execution and verification of the program and erase operations. the status read function is used to monitor the ready/ busy status of the device, determine the result (pass /fail) of a program or erase operation, and determine whether the device is in protect mode. the device status is output via the i/o port using re after a ?70h? command input. the status read can also be used during a read operation to find out the ready/busy status. the resulting information is outlined in table 6. table 6. status output table definition page program block erase read i/o1 chip status pass: 0 fail: 1 pass/fail pass/fail pass/fail(uncorrectable) i/o2 not used invalid invalid invalid i/o3 not used 0 0 0 i/o4 chip read status normal or uncorrectable: 0 recommended to rewrite : 1 0 0 normal or uncorrectable / recommended to rewrite i/o5 not used 0 0 0 i/o6 ready/busy ready: 1 busy: 0 ready/busy ready/busy ready/busy i/o7 ready/busy ready: 1 busy: 0 ready/busy ready/busy ready/busy i/o8 write protect not protected :1 protected: 0 write protect write protect write protect the pass/fail status on i/o1 is only valid during a program/erase operation when the device is in the ready state.
TC58BVG0S3HTAI0 2012-08-31c 31 ecc status read the ecc status read function is used to monitor th e error correction status. 24nm benand can correct up to 8bit errors. ecc can be performed on the nand flash main and sp are areas. the ecc status read function can also show the number of errors in a sector as a resu lt of an ecc check in during a read operation. 8 7 6 5 4 3 2 i/o1 sector infomation ecc status ecc status i/o4 to i/o1 ecc status 0000 no error 0001 1bit error(correctable) 0010 2bit error(correctable) 0011 3bit error(correctable) 0100 4bit error(correctable) 0101 5bit error(correctable) 0110 6bit error(correctable) 0111 7bit error(correctable) 1000 8bit error(correctable) 1111 uncorrectable error sector information i/o8 to i/o5 sector information 0000 1st sector (main and spare area) 0001 2nd sector (main and spare area) 0010 3rd sector (main and spare area) 0011 4th sector (main and spare area) other reserved
TC58BVG0S3HTAI0 2012-08-31c 32 reset the reset mode stops all operations. for example, in case of a program or erase operation, the internally generated voltage is discharged to 0 volt and the device enters the wait state. reset during a page copy may not just stop the most re cent page program but it may also stop the previous program to a page depending on when the ff reset is input. the response to a ?ffh? reset co mmand input during the various device operations is as follows: when a reset (ffh) command is input during programming internal v pp 80 10 ff 00 by/ry t rst (max 10 s)
TC58BVG0S3HTAI0 2012-08-31c 33 when a reset (ffh) command is input during erasing when a reset (ffh) command is input during read operation when a reset (ffh) command is input during ready when a status read command (70h) is input after a reset when two or more reset commands are input in succession 10 by/ry ff ff (3) (2) (1) the second command is invalid, but the third command is valid. ff ff ff i/o status : pass/fail pass : ready/busy ready ff 70 by/ry 00 ff 00 by/ry t rst (max 5 s) 30 internal erase voltage d0 ff 00 by/ry t rst (max 500 s) 00 by/ry t rst (max 5 s) ff
TC58BVG0S3HTAI0 2012-08-31c 34 application notes and comments (1) power-on/off sequence: the timing sequence shown in the figure below is necessary for the power-on/off sequence. the device internal initialization starts after the powe r supply reaches an appropriate level in the power on sequence. during the initialization th e device ready/busy signal indicates the busy state as shown in the figure below. in this time period, the acceptable commands are ffh or 70h. the wp signal is useful for protecting against data corruption at power-on/off. (2) power-on reset the following sequence is necessary because some input signals may not be stable at power-on. (3) prohibition of unspecified commands the operation commands are listed in t able 3. input of a command other th an those specified in table 3 is prohibited. stored data may be co rrupted if an unknown command is entered during the command cycle. (4) restriction of commands while in the busy state during the busy state, do not in put any command except 70h and ffh. ff reset power on v il operation 0 v v cc 2.7 v 2.5 v v il don?t care don?t care v ih ce , we , re wp cle, ale invalid invalid ready/busy 1 ms max 100 s max don?t care invalid 1 ms max 100 s max 1ms 2.7 v 2.5 v 0.5 v 0.5 v
TC58BVG0S3HTAI0 2012-08-31c 35 (5) acceptable commands after serial input command ?80h? once the serial input command ?80h ? has been input, do not input an y command other than the column address change in serial data input command ?85h?, auto program command ?10h? or the reset command ?ffh?. if a command other than ?85h? , ?10h? or ?ffh? is in put, the program operation is not performed and the device operation is set to the mode which the input co mmand specifies. (6) addressing for program operation within a block, the pages must be programmed consecut ively from the lsb (least significant bit) page of the block to msb (most significant bit) page of the bl ock. random page address programming is prohibited. data in: data (1) page 0 data register page 2 page 1 page 31 page 63 (1) (2) (3) (32) (64) data (64) from the lsb page to msb page data in: data (1) page 0 data register page 2 page 1 page 31 page 63 (2) (32) (3) (1) (64) data (64) ex.) random page program (prohibition) command other than ?85h?, ?10h? or ?ffh? 80 programming cannot be executed. 10 xx mode specified by the command. we by/ry 80 ff address input
TC58BVG0S3HTAI0 2012-08-31c 36 (7) status read during a read operation the device status can be read out by inputting the status read command ?70h? in read mode. once the device has been set to status read mode by a ?70h ? command, the device will not return to read mode unless the read command ?00h? is inputted during [a]. if the read command ?00h? is inputted during [a], status read mode is reset, and the device returns to read mode. in this ca se, data output starts automatically from address n and address input is unnecessary (8) auto programming failure (9) by/ry : termination for the ready/busy pin ( by/ry ) a pull-up resistor needs to be used for termination because the by/ry buffer consists of an open drain circuit. fail 80 10 80 10 address m data input 70 i/o address n data input if the programming result for page address m is fail, do not try to program the page to address n in another block without the data input sequence. because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary. 10 80 m n this data may vary fr om device to device. we recommend that you use this data as a reference when selecting a resistor value. v cc v cc device v ss r by/ry c l 1.5 s 1.0 s 0.5 s 0 1 k ? 4 k ? 3 k ? 2 k ? 15 ns 10 ns 5 ns t f t r r t r t f v cc = 3.3 v ta = 25c c l = 50 pf t f ready v cc t r busy status read . 00 address n command ce we by/ry re [a] status read command input status output 70 00 30
TC58BVG0S3HTAI0 2012-08-31c 37 (10) note regarding the wp signal the erase and program operations are automatically reset when wp goes low. the operations are enabled and disabled as follows: enable programming disable programming enable erasing disable erasing wp t ww (100 ns min) 80 10 we by/ry din wp t ww (100 ns min) 60 d0 we by/ry din wp t ww (100 ns min) 80 10 we by/ry din wp t ww (100 ns min) 60 d0 we by/ry din
TC58BVG0S3HTAI0 2012-08-31c 38 (11) when five address cycles are input although the device may read in a fifth address, it is ignored inside the chip. read operation program operation cle address input 00h ce we ale i/o by/ry ignored 30h cle ce we ale i/o address input ignored 80h data input
TC58BVG0S3HTAI0 2012-08-31c 39 (12) several programming cycles on the same page (partial page program) each segment can be programme d individually as follows: data pattern 4 data pattern 1 all 1 s all 1 s all 1 s all 1 s 1st programming 2nd programming 4th programming result data pattern 1 data pattern 2 data pattern 4 data pattern 2
TC58BVG0S3HTAI0 2012-08-31c 40 (13) invalid blocks (bad blocks) the device occasionally contains unusable blocks. therefore, the following issues must be recognized: please do not perform an erase op eration to bad blocks. it may be impossible to recover the bad block information if the information is erased. check if the device has any bad blocks after installation into the system. refer to the test flow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by the system. a bad block does not affect the perfor mance of good blocks because it is isolated from the bit lines by select gates. the number of valid blocks over th e device lifetime is as follows: min typ. max unit valid (good) block number 1004 ? 1024 block bad block test flow regarding invalid blocks, bad bl ock mark is in whole pages. please read one column of any page in each block. if th e data of the column is 00 (hex), define the block as a bad block * 1: no erase operation is allowed to detected bad blocks bad block bad block pass read check start entry bad block * 1 last block end yes fail block no = 1 no block no. = block no. + 1
TC58BVG0S3HTAI0 2012-08-31c 41 (14) failure phenomena for prog ram and erase operations the device may fail during a program or erase operation. the following possible failure modes should be consid ered when implementing a highly reliable system. failure mode detection and countermeasure sequence block erase failure status read after erase block replacement page programming failure status read after program block replacement read 9bit failure(uncorrectable error) uncorrectable ecc error ? ecc: error correction code. 8 bit correction per 528bytes is executed in a device. ? block replacement program erase when an error occurs during an erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) do not turn off the power before write/erase operation is complete. avoid using th e device when the battery is low. power shortage and/or power failure before wr ite/erase operation is complete will cause loss of data and/or damage to data. when an error happens in block a, try to reprogram the data into another block (block b) by loading from an external buffer. then, prevent further system accesses to block a ( by creating a bad block table or by using another appropriate scheme). block a block b error occurs buffer memory
TC58BVG0S3HTAI0 2012-08-31c 42 package dimensions weight: 0.53g (typ.)
TC58BVG0S3HTAI0 2012-08-31c 43 revision history date rev. description 2012-02-17 0.10 preliminary version 2012-07-06 0.20 changed tberase. revi sed id table. corrected typo. 2012-08-31 1.00 deleted tentative/tbd notation.
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